4
Instructions
Outline
The MOP-GL240128D
is controlled using a standard T6963
compliant controller. The display is enabled
by pulling
the Chip Select (CS) pin
low, communication to and from the device is controlled using the
active low Write (WR) and Read (RD)
inputs, and the unit may be reset by pulling the RST line low.
Using
Register Select, either the Command
Register (C)
or Data Register (D)
is
selected
by toggling C/D high or
low respectively.
Before any data is read or written, the status of the display controller must be read. This is
accomplished by setting RD low, WR high, CS low, C/D high, and reading the status byte that appears on
the data lines. Each bit of the status word indicates a specific condition, outlined below.
Table 3:
Status Bits
Bit
Description
Status
D0
Command execution capability.
0:Disabled, 1:Enabled.
D1
Data read/write capability.
0:Disabled, 1:Enabled.
D2
Auto mode data read capability.
0:Disabled, 1:Enabled.
D3
Auto mode data write capability.
0:Disabled, 1:Enabled.
D4
Unused.
Unused.
D5
Controller operation capability.
0:Disabled, 1:Enabled.
D6
Screen peek/copy error flag.
0:No Error, 1:Error.
D7
Blink condition.
0:Display Off, 1:Normal Display.
The first two bits, D0 and D1, should be read at the same time. In auto mode, D2 and D3 become valid
while D0 and D1 are invalid. The display should be in an enabled condition before commands or data
are transmitted. Data bytes are transferred before commands, as shown below.
Figure 2: Single Byte Command
Figure 3: Two Byte Command
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